accelerometer.cpp

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#include "drivers/accelerometer.h"
 
Accelerometer::Accelerometer()
{
}
 
Accelerometer::Accelerometer(TwoWire *wire, BinarySemaphore *wireLock, uint8_t i2c_address)
{
    _wire = wire;
    _wireLock = wireLock;
    _i2c_address = i2c_address;
  // Reset scroll filter array;
  for(uint8_t scrl=0; scrl<ARR_REG_FILTER; scrl++) {
    _raw_scroll[0][scrl] = INT16_MAX;
    _raw_scroll[1][scrl] = INT16_MAX;
    _raw_scroll[2][scrl] = INT16_MAX;
  }
}
 
int32_t Accelerometer::iis328dq_read_reg(uint8_t reg, uint8_t *data, uint16_t len)
{
  // Try lock Semaphore
    if (_wireLock->Take(Ticks::MsToTicks(ACCELEROMETER_SEMAPHORE_MAX_WAITING_TIME_MS)))
    {
    /* Read multiple command */
    reg |= 0x80;
    _wire->beginTransmission(_i2c_address);
    _wire->write(reg);
    _wire->endTransmission();
    _wire->beginTransmission(_i2c_address);
    _wire->requestFrom(_i2c_address, len);
    for(uint8_t i=0; i<len; i++)
      *(data + i) = _wire->read();
    _wire->endTransmission();
        _wireLock->Give();
    return 0;
  } else 
    return 1;
}
 
int32_t Accelerometer::iis328dq_write_reg(uint8_t reg, uint8_t *data, uint16_t len)
{
  // Try lock Semaphore
    if (_wireLock->Take(Ticks::MsToTicks(ACCELEROMETER_SEMAPHORE_MAX_WAITING_TIME_MS)))
    {
    // /* Write multiple command */
    reg|=0x80;
    _wire->beginTransmission(_i2c_address);
    _wire->write(reg);
    for(uint8_t i=0; i<len; i++)
      _wire->write(*(data + i));
    _wire->endTransmission();
        _wireLock->Give();
    return 0;
  } else
    return 1;
}
 
void Accelerometer::push_raw_data(int16_t *data_raw)
{
  // Scroll Value
  for(uint8_t i = (ARR_REG_FILTER-1); i>0; i--) {
    _raw_scroll[0][i] = _raw_scroll[0][i-1];
    _raw_scroll[1][i] = _raw_scroll[1][i-1];
    _raw_scroll[2][i] = _raw_scroll[2][i-1];
  }
  // Add New
  _raw_scroll[0][0] = data_raw[0];
  _raw_scroll[1][0] = data_raw[1];
  _raw_scroll[2][0] = data_raw[2];
}
 
int16_t Accelerometer::get_raw_mean(coordinate request) {
  uint32_t tmp_data = 0;
  uint8_t tmp_count = 0;
  for(uint8_t i=0; i<ARR_REG_FILTER; i++) {
    if((_raw_scroll[request][i]>=-16000) && (_raw_scroll[request][i]<=16000)) {
      tmp_data += _raw_scroll[request][i];
      tmp_count++;
    }
  }
  return (int16_t) (tmp_data / tmp_count);
}
 
float_t Accelerometer::iis328dq_from_fs2_to_mg(int16_t lsb)
{
  return ((float_t)lsb * 0.98f / 16.0f);
}
 
float_t Accelerometer::iis328dq_from_fs2_to_mg(coordinate request)
{
  return ((float_t)get_raw_mean(request) * 0.98f / 16.0f);
}
 
float_t Accelerometer::iis328dq_from_fs4_to_mg(int16_t lsb)
{
  return ((float_t)lsb * 1.95f / 16.0f);
}
 
float_t Accelerometer::iis328dq_from_fs4_to_mg(coordinate request)
{
  return ((float_t)get_raw_mean(request) * 1.95f / 16.0f);
}
 
float_t Accelerometer::iis328dq_from_fs8_to_mg(int16_t lsb)
{
  return ((float_t)lsb * 3.91f / 16.0f);
}
 
float_t Accelerometer::iis328dq_from_fs8_to_mg(coordinate request)
{
  return ((float_t)get_raw_mean(request) * 3.91f / 16.0f);
}
 
float_t Accelerometer::iis328dq_from_fsx_to_inc(int16_t lsb)
{
  return ((float_t)lsb / 16000.0f);
}
 
float_t Accelerometer::iis328dq_from_fsx_to_inc(coordinate request)
{
  return ((float_t)get_raw_mean(request) / 16000.0f);
}
 
int32_t Accelerometer::iis328dq_axis_x_data_set(uint8_t val)
{
  iis328dq_ctrl_reg1_t ctrl_reg1;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG1,
                          (uint8_t *)&ctrl_reg1, 1);
 
  if (ret == 0)
  {
    ctrl_reg1.xen = val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG1,
                             (uint8_t *)&ctrl_reg1, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_axis_x_data_get(uint8_t *val)
{
  iis328dq_ctrl_reg1_t ctrl_reg1;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG1,
                          (uint8_t *)&ctrl_reg1, 1);
  *val = ctrl_reg1.xen;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_axis_y_data_set(uint8_t val)
{
  iis328dq_ctrl_reg1_t ctrl_reg1;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG1,
                          (uint8_t *)&ctrl_reg1, 1);
 
  if (ret == 0)
  {
    ctrl_reg1.yen = val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG1,
                             (uint8_t *)&ctrl_reg1, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_axis_y_data_get(uint8_t *val)
{
  iis328dq_ctrl_reg1_t ctrl_reg1;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG1,
                          (uint8_t *)&ctrl_reg1, 1);
  *val = ctrl_reg1.yen;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_axis_z_data_set(uint8_t val)
{
  iis328dq_ctrl_reg1_t ctrl_reg1;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG1,
                          (uint8_t *)&ctrl_reg1, 1);
 
  if (ret == 0)
  {
    ctrl_reg1.zen = val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG1,
                             (uint8_t *)&ctrl_reg1, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_axis_z_data_get(uint8_t *val)
{
  iis328dq_ctrl_reg1_t ctrl_reg1;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG1,
                          (uint8_t *)&ctrl_reg1, 1);
  *val = ctrl_reg1.zen;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_data_rate_set(iis328dq_dr_t val)
{
  iis328dq_ctrl_reg1_t ctrl_reg1;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG1,
                          (uint8_t *)&ctrl_reg1, 1);
 
  if (ret == 0)
  {
    ctrl_reg1.pm = (uint8_t)val & 0x07U;
    ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG1,
                             (uint8_t *)&ctrl_reg1, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_data_rate_get(iis328dq_dr_t *val)
{
  iis328dq_ctrl_reg1_t ctrl_reg1;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG1,
                          (uint8_t *)&ctrl_reg1, 1);
 
  switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
  {
    case IIS328DQ_ODR_OFF:
      *val = IIS328DQ_ODR_OFF;
      break;
 
    case IIS328DQ_ODR_Hz5:
      *val = IIS328DQ_ODR_Hz5;
      break;
 
    case IIS328DQ_ODR_1Hz:
      *val = IIS328DQ_ODR_1Hz;
      break;
 
    case IIS328DQ_ODR_5Hz2:
      *val = IIS328DQ_ODR_5Hz2;
      break;
 
    case IIS328DQ_ODR_5Hz:
      *val = IIS328DQ_ODR_5Hz;
      break;
 
    case IIS328DQ_ODR_10Hz:
      *val = IIS328DQ_ODR_10Hz;
      break;
 
    case IIS328DQ_ODR_50Hz:
      *val = IIS328DQ_ODR_50Hz;
      break;
 
    case IIS328DQ_ODR_100Hz:
      *val = IIS328DQ_ODR_100Hz;
      break;
 
    case IIS328DQ_ODR_400Hz:
      *val = IIS328DQ_ODR_400Hz;
      break;
 
    case IIS328DQ_ODR_1kHz:
      *val = IIS328DQ_ODR_1kHz;
      break;
 
    default:
      *val = IIS328DQ_ODR_OFF;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_reference_mode_set(iis328dq_hpm_t val)
{
  iis328dq_ctrl_reg2_t ctrl_reg2;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG2,
                          (uint8_t *)&ctrl_reg2, 1);
 
  if (ret == 0)
  {
    ctrl_reg2.hpm = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG2,
                             (uint8_t *)&ctrl_reg2, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_reference_mode_get(iis328dq_hpm_t *val)
{
  iis328dq_ctrl_reg2_t ctrl_reg2;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG2,
                          (uint8_t *)&ctrl_reg2, 1);
 
  switch (ctrl_reg2.hpm)
  {
    case IIS328DQ_NORMAL_MODE:
      *val = IIS328DQ_NORMAL_MODE;
      break;
 
    case IIS328DQ_REF_MODE_ENABLE:
      *val = IIS328DQ_REF_MODE_ENABLE;
      break;
 
    default:
      *val = IIS328DQ_NORMAL_MODE;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_full_scale_set(iis328dq_fs_t val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  if (ret == 0)
  {
    ctrl_reg4.fs = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG4,
                             (uint8_t *)&ctrl_reg4, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_full_scale_get(iis328dq_fs_t *val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  switch (ctrl_reg4.fs)
  {
    case IIS328DQ_2g:
      *val = IIS328DQ_2g;
      break;
 
    case IIS328DQ_4g:
      *val = IIS328DQ_4g;
      break;
 
    case IIS328DQ_8g:
      *val = IIS328DQ_8g;
      break;
 
    default:
      *val = IIS328DQ_2g;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_block_data_update_set(uint8_t val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  if (ret == 0)
  {
    ctrl_reg4.bdu = val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG4,
                             (uint8_t *)&ctrl_reg4, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_block_data_update_get(uint8_t *val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
  *val = ctrl_reg4.bdu;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_status_reg_get(iis328dq_status_reg_t *val)
{
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_STATUS_REG, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_flag_data_ready_get(uint8_t *val)
{
  iis328dq_status_reg_t status_reg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_STATUS_REG,
                          (uint8_t *)&status_reg, 1);
  *val = status_reg.zyxda;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_acceleration_raw_get(int16_t *val)
{
  uint8_t buff[6];
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_OUT_X_L, buff, 6);
  val[0] = (int16_t)buff[1];
  val[0] = (val[0] * 256) + (int16_t)buff[0];
  val[1] = (int16_t)buff[3];
  val[1] = (val[1] * 256) + (int16_t)buff[2];
  val[2] = (int16_t)buff[5];
  val[2] = (val[2] * 256) + (int16_t)buff[4];
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_device_id_get(uint8_t *buff)
{
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_WHO_AM_I, buff, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_boot_set(uint8_t val)
{
  iis328dq_ctrl_reg2_t ctrl_reg2;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG2,
                          (uint8_t *)&ctrl_reg2, 1);
 
  if (ret == 0)
  {
    ctrl_reg2.boot = val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG2,
                             (uint8_t *)&ctrl_reg2, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_boot_get(uint8_t *val)
{
  iis328dq_ctrl_reg2_t ctrl_reg2;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG2,
                          (uint8_t *)&ctrl_reg2, 1);
  *val = ctrl_reg2.boot;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_self_test_set(iis328dq_st_t val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  if (ret == 0)
  {
    ctrl_reg4.st = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG4,
                             (uint8_t *)&ctrl_reg4, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_self_test_get(iis328dq_st_t *val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  switch (ctrl_reg4.st)
  {
    case IIS328DQ_ST_DISABLE:
      *val = IIS328DQ_ST_DISABLE;
      break;
 
    case IIS328DQ_ST_POSITIVE:
      *val = IIS328DQ_ST_POSITIVE;
      break;
 
    case IIS328DQ_ST_NEGATIVE:
      *val = IIS328DQ_ST_NEGATIVE;
      break;
 
    default:
      *val = IIS328DQ_ST_DISABLE;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_data_format_set(iis328dq_ble_t val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  if (ret == 0)
  {
    ctrl_reg4.ble = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG4,
                             (uint8_t *)&ctrl_reg4, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_data_format_get(iis328dq_ble_t *val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  switch (ctrl_reg4.ble)
  {
    case IIS328DQ_LSB_AT_LOW_ADD:
      *val = IIS328DQ_LSB_AT_LOW_ADD;
      break;
 
    case IIS328DQ_MSB_AT_LOW_ADD:
      *val = IIS328DQ_MSB_AT_LOW_ADD;
      break;
 
    default:
      *val = IIS328DQ_LSB_AT_LOW_ADD;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_hp_bandwidth_set(iis328dq_hpcf_t val)
{
  iis328dq_ctrl_reg2_t ctrl_reg2;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG2,
                          (uint8_t *)&ctrl_reg2, 1);
 
  if (ret == 0)
  {
    ctrl_reg2.hpcf = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG2,
                             (uint8_t *)&ctrl_reg2, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_hp_bandwidth_get(iis328dq_hpcf_t *val)
{
  iis328dq_ctrl_reg2_t ctrl_reg2;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG2,
                          (uint8_t *)&ctrl_reg2, 1);
 
  switch (ctrl_reg2.hpcf)
  {
    case IIS328DQ_CUT_OFF_8Hz:
      *val = IIS328DQ_CUT_OFF_8Hz;
      break;
 
    case IIS328DQ_CUT_OFF_16Hz:
      *val = IIS328DQ_CUT_OFF_16Hz;
      break;
 
    case IIS328DQ_CUT_OFF_32Hz:
      *val = IIS328DQ_CUT_OFF_32Hz;
      break;
 
    case IIS328DQ_CUT_OFF_64Hz:
      *val = IIS328DQ_CUT_OFF_64Hz;
      break;
 
    default:
      *val = IIS328DQ_CUT_OFF_8Hz;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_hp_path_set(iis328dq_hpen_t val)
{
  iis328dq_ctrl_reg2_t ctrl_reg2;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG2,
                          (uint8_t *)&ctrl_reg2, 1);
 
  if (ret == 0)
  {
    ctrl_reg2.hpen = (uint8_t)val & 0x03U;
    ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG2,
                             (uint8_t *)&ctrl_reg2, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_hp_path_get(iis328dq_hpen_t *val)
{
  iis328dq_ctrl_reg2_t ctrl_reg2;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG2,
                          (uint8_t *)&ctrl_reg2, 1);
 
  switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
  {
    case IIS328DQ_HP_DISABLE:
      *val = IIS328DQ_HP_DISABLE;
      break;
 
    case IIS328DQ_HP_ON_OUT:
      *val = IIS328DQ_HP_ON_OUT;
      break;
 
    case IIS328DQ_HP_ON_INT1:
      *val = IIS328DQ_HP_ON_INT1;
      break;
 
    case IIS328DQ_HP_ON_INT2:
      *val = IIS328DQ_HP_ON_INT2;
      break;
 
    case IIS328DQ_HP_ON_INT1_INT2:
      *val = IIS328DQ_HP_ON_INT1_INT2;
      break;
 
    case IIS328DQ_HP_ON_INT1_INT2_OUT:
      *val = IIS328DQ_HP_ON_INT1_INT2_OUT;
      break;
 
    case IIS328DQ_HP_ON_INT2_OUT:
      *val = IIS328DQ_HP_ON_INT2_OUT;
      break;
 
    case IIS328DQ_HP_ON_INT1_OUT:
      *val = IIS328DQ_HP_ON_INT1_OUT;
      break;
 
    default:
      *val = IIS328DQ_HP_DISABLE;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_hp_reset_get(void)
{
  uint8_t dummy;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_HP_FILTER_RESET,
                          (uint8_t *)&dummy, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_hp_reference_value_set(uint8_t val)
{
  int32_t ret;
 
  ret = iis328dq_write_reg(IIS328DQ_REFERENCE, (uint8_t *)&val, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_hp_reference_value_get(uint8_t *val)
{
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_REFERENCE, val, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_spi_mode_set(iis328dq_sim_t val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  if (ret == 0)
  {
    ctrl_reg4.sim = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG4,
                             (uint8_t *)&ctrl_reg4, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_spi_mode_get(iis328dq_sim_t *val)
{
  iis328dq_ctrl_reg4_t ctrl_reg4;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG4,
                          (uint8_t *)&ctrl_reg4, 1);
 
  switch (ctrl_reg4.sim)
  {
    case IIS328DQ_SPI_4_WIRE:
      *val = IIS328DQ_SPI_4_WIRE;
      break;
 
    case IIS328DQ_SPI_3_WIRE:
      *val = IIS328DQ_SPI_3_WIRE;
      break;
 
    default:
      *val = IIS328DQ_SPI_4_WIRE;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_pin_int1_route_set(iis328dq_i1_cfg_t val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  if (ret == 0)
  {
    ctrl_reg3.i1_cfg = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG3,
                             (uint8_t *)&ctrl_reg3, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_pin_int1_route_get(iis328dq_i1_cfg_t *val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  switch (ctrl_reg3.i1_cfg)
  {
    case IIS328DQ_PAD1_INT1_SRC:
      *val = IIS328DQ_PAD1_INT1_SRC;
      break;
 
    case IIS328DQ_PAD1_INT1_OR_INT2_SRC:
      *val = IIS328DQ_PAD1_INT1_OR_INT2_SRC;
      break;
 
    case IIS328DQ_PAD1_DRDY:
      *val = IIS328DQ_PAD1_DRDY;
      break;
 
    case IIS328DQ_PAD1_BOOT:
      *val = IIS328DQ_PAD1_BOOT;
      break;
 
    default:
      *val = IIS328DQ_PAD1_INT1_SRC;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_notification_set(iis328dq_lir1_t val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  if (ret == 0)
  {
    ctrl_reg3.lir1 = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG3,
                             (uint8_t *)&ctrl_reg3, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_notification_get(iis328dq_lir1_t *val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  switch (ctrl_reg3.lir1)
  {
    case IIS328DQ_INT1_PULSED:
      *val = IIS328DQ_INT1_PULSED;
      break;
 
    case IIS328DQ_INT1_LATCHED:
      *val = IIS328DQ_INT1_LATCHED;
      break;
 
    default:
      *val = IIS328DQ_INT1_PULSED;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_pin_int2_route_set(iis328dq_i2_cfg_t val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  if (ret == 0)
  {
    ctrl_reg3.i2_cfg = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG3,
                             (uint8_t *)&ctrl_reg3, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_pin_int2_route_get(iis328dq_i2_cfg_t *val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  switch (ctrl_reg3.i2_cfg)
  {
    case IIS328DQ_PAD2_INT2_SRC:
      *val = IIS328DQ_PAD2_INT2_SRC;
      break;
 
    case IIS328DQ_PAD2_INT1_OR_INT2_SRC:
      *val = IIS328DQ_PAD2_INT1_OR_INT2_SRC;
      break;
 
    case IIS328DQ_PAD2_DRDY:
      *val = IIS328DQ_PAD2_DRDY;
      break;
 
    case IIS328DQ_PAD2_BOOT:
      *val = IIS328DQ_PAD2_BOOT;
      break;
 
    default:
      *val = IIS328DQ_PAD2_INT2_SRC;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_notification_set(iis328dq_lir2_t val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  if (ret == 0)
  {
    ctrl_reg3.lir2 = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG3,
                             (uint8_t *)&ctrl_reg3, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_notification_get(iis328dq_lir2_t *val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  switch (ctrl_reg3.lir2)
  {
    case IIS328DQ_INT2_PULSED:
      *val = IIS328DQ_INT2_PULSED;
      break;
 
    case IIS328DQ_INT2_LATCHED:
      *val = IIS328DQ_INT2_LATCHED;
      break;
 
    default:
      *val = IIS328DQ_INT2_PULSED;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_pin_mode_set(iis328dq_pp_od_t val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  if (ret == 0)
  {
    ctrl_reg3.pp_od = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG3,
                             (uint8_t *)&ctrl_reg3, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_pin_mode_get(iis328dq_pp_od_t *val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  switch (ctrl_reg3.pp_od)
  {
    case IIS328DQ_PUSH_PULL:
      *val = IIS328DQ_PUSH_PULL;
      break;
 
    case IIS328DQ_OPEN_DRAIN:
      *val = IIS328DQ_OPEN_DRAIN;
      break;
 
    default:
      *val = IIS328DQ_PUSH_PULL;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_pin_polarity_set(iis328dq_ihl_t val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  if (ret == 0)
  {
    ctrl_reg3.ihl = (uint8_t)val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG3,
                             (uint8_t *)&ctrl_reg3, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_pin_polarity_get(iis328dq_ihl_t *val)
{
  iis328dq_ctrl_reg3_t ctrl_reg3;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG3,
                          (uint8_t *)&ctrl_reg3, 1);
 
  switch (ctrl_reg3.ihl)
  {
    case IIS328DQ_ACTIVE_HIGH:
      *val = IIS328DQ_ACTIVE_HIGH;
      break;
 
    case IIS328DQ_ACTIVE_LOW:
      *val = IIS328DQ_ACTIVE_LOW;
      break;
 
    default:
      *val = IIS328DQ_ACTIVE_HIGH;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_on_threshold_conf_set(int1_on_th_conf_t val)
{
  iis328dq_int1_cfg_t int1_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
 
  if (ret == 0)
  {
    int1_cfg.xlie  = val.int1_xlie;
    int1_cfg.xhie  = val.int1_xhie;
    int1_cfg.ylie  = val.int1_ylie;
    int1_cfg.yhie  = val.int1_yhie;
    int1_cfg.zlie  = val.int1_zlie;
    int1_cfg.zhie  = val.int1_zhie;
    ret = iis328dq_write_reg(IIS328DQ_INT1_CFG,
                             (uint8_t *)&int1_cfg, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_on_threshold_conf_get(int1_on_th_conf_t *val)
{
  iis328dq_int1_cfg_t int1_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
  val->int1_xlie = int1_cfg.xlie;
  val->int1_xhie = int1_cfg.xhie;
  val->int1_ylie = int1_cfg.ylie;
  val->int1_yhie = int1_cfg.yhie;
  val->int1_zlie = int1_cfg.zlie;
  val->int1_zhie = int1_cfg.zhie;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_on_threshold_mode_set(iis328dq_int1_aoi_t val)
{
  iis328dq_int1_cfg_t int1_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
 
  if (ret == 0)
  {
    int1_cfg.aoi = (uint8_t) val;
    ret = iis328dq_write_reg(IIS328DQ_INT1_CFG,
                             (uint8_t *)&int1_cfg, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_on_threshold_mode_get(iis328dq_int1_aoi_t *val)
{
  iis328dq_int1_cfg_t int1_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
 
  switch (int1_cfg.aoi)
  {
    case IIS328DQ_INT1_ON_THRESHOLD_OR:
      *val = IIS328DQ_INT1_ON_THRESHOLD_OR;
      break;
 
    case IIS328DQ_INT1_ON_THRESHOLD_AND:
      *val = IIS328DQ_INT1_ON_THRESHOLD_AND;
      break;
 
    default:
      *val = IIS328DQ_INT1_ON_THRESHOLD_OR;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_src_get(iis328dq_int1_src_t *val)
{
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_SRC, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_treshold_set(uint8_t val)
{
  iis328dq_int1_ths_t int1_ths;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
 
  if (ret == 0)
  {
    int1_ths.ths = val;
    ret = iis328dq_write_reg(IIS328DQ_INT1_THS,
                             (uint8_t *)&int1_ths, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_treshold_get(uint8_t *val)
{
  iis328dq_int1_ths_t int1_ths;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
  *val = int1_ths.ths;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_dur_set(uint8_t val)
{
  iis328dq_int1_duration_t int1_duration;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_DURATION,
                          (uint8_t *)&int1_duration, 1);
 
  if (ret == 0)
  {
    int1_duration.d = val;
    ret = iis328dq_write_reg(IIS328DQ_INT1_DURATION,
                             (uint8_t *)&int1_duration, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_dur_get(uint8_t *val)
{
  iis328dq_int1_duration_t int1_duration;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_DURATION,
                          (uint8_t *)&int1_duration, 1);
  *val = int1_duration.d;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_on_threshold_conf_set(int2_on_th_conf_t val)
{
  iis328dq_int2_cfg_t int2_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_CFG,
                          (uint8_t *)&int2_cfg, 1);
 
  if (ret == 0)
  {
    int2_cfg.xlie  = val.int2_xlie;
    int2_cfg.xhie  = val.int2_xhie;
    int2_cfg.ylie  = val.int2_ylie;
    int2_cfg.yhie  = val.int2_yhie;
    int2_cfg.zlie  = val.int2_zlie;
    int2_cfg.zhie  = val.int2_zhie;
    ret = iis328dq_write_reg(IIS328DQ_INT2_CFG,
                             (uint8_t *)&int2_cfg, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_on_threshold_conf_get(int2_on_th_conf_t *val)
{
  iis328dq_int2_cfg_t int2_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
  val->int2_xlie = int2_cfg.xlie;
  val->int2_xhie = int2_cfg.xhie;
  val->int2_ylie = int2_cfg.ylie;
  val->int2_yhie = int2_cfg.yhie;
  val->int2_zlie = int2_cfg.zlie;
  val->int2_zhie = int2_cfg.zhie;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_on_threshold_mode_set(iis328dq_int2_aoi_t val)
{
  iis328dq_int2_cfg_t int2_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
 
  if (ret == 0)
  {
    int2_cfg.aoi = (uint8_t) val;
    ret = iis328dq_write_reg(IIS328DQ_INT2_CFG,
                             (uint8_t *)&int2_cfg, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_on_threshold_mode_get(iis328dq_int2_aoi_t *val)
{
  iis328dq_int2_cfg_t int2_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
 
  switch (int2_cfg.aoi)
  {
    case IIS328DQ_INT2_ON_THRESHOLD_OR:
      *val = IIS328DQ_INT2_ON_THRESHOLD_OR;
      break;
 
    case IIS328DQ_INT2_ON_THRESHOLD_AND:
      *val = IIS328DQ_INT2_ON_THRESHOLD_AND;
      break;
 
    default:
      *val = IIS328DQ_INT2_ON_THRESHOLD_OR;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_src_get(iis328dq_int2_src_t *val)
{
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_SRC, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_treshold_set(uint8_t val)
{
  iis328dq_int2_ths_t int2_ths;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
 
  if (ret == 0)
  {
    int2_ths.ths = val;
    ret = iis328dq_write_reg(IIS328DQ_INT2_THS,
                             (uint8_t *)&int2_ths, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_treshold_get(uint8_t *val)
{
  iis328dq_int2_ths_t int2_ths;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
  *val = int2_ths.ths;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_dur_set(uint8_t val)
{
  iis328dq_int2_duration_t int2_duration;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_DURATION,
                          (uint8_t *)&int2_duration, 1);
 
  if (ret == 0)
  {
    int2_duration.d = val;
    ret = iis328dq_write_reg(IIS328DQ_INT2_DURATION,
                             (uint8_t *)&int2_duration, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_dur_get(uint8_t *val)
{
  iis328dq_int2_duration_t int2_duration;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_DURATION,
                          (uint8_t *)&int2_duration, 1);
  *val = int2_duration.d;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_wkup_to_sleep_set(uint8_t val)
{
  iis328dq_ctrl_reg5_t ctrl_reg5;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG5,
                          (uint8_t *)&ctrl_reg5, 1);
 
  if (ret == 0)
  {
    ctrl_reg5.turnon = val;
    ret = iis328dq_write_reg(IIS328DQ_CTRL_REG5,
                             (uint8_t *)&ctrl_reg5, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_wkup_to_sleep_get(uint8_t *val)
{
  iis328dq_ctrl_reg5_t ctrl_reg5;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_CTRL_REG5,
                          (uint8_t *)&ctrl_reg5, 1);
  *val = ctrl_reg5.turnon;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_6d_mode_set(iis328dq_int1_6d_t val)
{
  iis328dq_int1_cfg_t int1_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
 
  if (ret == 0)
  {
    int1_cfg._6d = (uint8_t)val & 0x01U;
    int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
    ret = iis328dq_write_reg(IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_6d_mode_get(iis328dq_int1_6d_t *val)
{
  iis328dq_int1_cfg_t int1_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
 
  switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
  {
    case IIS328DQ_6D_INT1_DISABLE:
      *val = IIS328DQ_6D_INT1_DISABLE;
      break;
 
    case IIS328DQ_6D_INT1_MOVEMENT:
      *val = IIS328DQ_6D_INT1_MOVEMENT;
      break;
 
    case IIS328DQ_6D_INT1_POSITION:
      *val = IIS328DQ_6D_INT1_POSITION;
      break;
 
    default:
      *val = IIS328DQ_6D_INT1_DISABLE;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_6d_src_get(iis328dq_int1_src_t *val)
{
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_SRC, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_6d_treshold_set(uint8_t val)
{
  iis328dq_int1_ths_t int1_ths;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
 
  if (ret == 0)
  {
    int1_ths.ths = val;
    ret = iis328dq_write_reg(IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int1_6d_treshold_get(uint8_t *val)
{
  iis328dq_int1_ths_t int1_ths;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
  *val = int1_ths.ths;
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_6d_mode_set(iis328dq_int2_6d_t val)
{
  iis328dq_int2_cfg_t int2_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
 
  if (ret == 0)
  {
    int2_cfg._6d = (uint8_t)val & 0x01U;
    int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
    ret = iis328dq_write_reg(IIS328DQ_INT2_CFG,
                             (uint8_t *)&int2_cfg, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_6d_mode_get(iis328dq_int2_6d_t *val)
{
  iis328dq_int2_cfg_t int2_cfg;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
 
  switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
  {
    case IIS328DQ_6D_INT2_DISABLE:
      *val = IIS328DQ_6D_INT2_DISABLE;
      break;
 
    case IIS328DQ_6D_INT2_MOVEMENT:
      *val = IIS328DQ_6D_INT2_MOVEMENT;
      break;
 
    case IIS328DQ_6D_INT2_POSITION:
      *val = IIS328DQ_6D_INT2_POSITION;
      break;
 
    default:
      *val = IIS328DQ_6D_INT2_DISABLE;
      break;
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_6d_src_get(iis328dq_int2_src_t *val)
{
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_SRC, (uint8_t *) val, 1);
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_6d_treshold_set(uint8_t val)
{
  iis328dq_int2_ths_t int2_ths;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
 
  if (ret == 0)
  {
    int2_ths.ths = val;
    ret = iis328dq_write_reg(IIS328DQ_INT2_THS,
                             (uint8_t *)&int2_ths, 1);
  }
 
  return ret;
}
 
int32_t Accelerometer::iis328dq_int2_6d_treshold_get(uint8_t *val)
{
  iis328dq_int2_ths_t int2_ths;
  int32_t ret;
 
  ret = iis328dq_read_reg(IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
  *val = int2_ths.ths;
 
  return ret;
}